GitHub

GitHub - Mohammad-Shadman/RISC-V-emulator: PipeLined Risc-V processor in verilog

This is expected as the probe signals are missing and need to be filled in. Once you have the probe signals setup, you should see a pd.vcd waveform file generated that you can view using gtkwave or ...
GitHub

HTL8254 82C54 Compatible Programmable Interval Timer IP core

The HTL8254 IP core is written in vendor neutral VHDL and as such can be simulated by any simulation tool. The testbench however uses Siemens’ Modelsim SignalSpy in order to provide a non-intrusive ...