note

浮動小数点数と少し仲良くなるためのまとめ【IEEE 754】

シンプレクス Advent Calendar 2025の24日目です。 こんにちは。シンプレクスでアプリケーション開発を行っている北川です。主に金融機関向けのリスク計測のシステム等の開発を担当してきました。 本記事では、計算処理で頻出する割に何かと振り回されがちな ...
GitHub

IEEE 754 Double Precision Floating Point Subtractor

A SystemVerilog implementation of an IEEE 754 double-precision floating point subtractor, verified at RTL level and pushed through full ASIC physical design using the OpenLane flow on the sky130 PDK.
IEEE

On the Compressibility of Floating-Point Data in Posit and IEEE-754 Representation

Abstract: The IEEE 754 floating-point standard is the most used representation for real numbers in modern computer systems, despite issues in accuracy for certain applications. The posit format, which ...
Embedded

Hardware-based floating-point design flow

Beforediscussing a new approach that enables floating-point implementation inhardware with performance similar to that of fixed-point processing, it isfirst necessary to discuss the reason why ...
EDN

Tutorial: Floating-point arithmetic on FPGAs

[Editor's note: For an intro to fixed-point math, see Fixed-Point DSP and Algorithm Implementation. For a comparison of fixed- and floating-point hardware, see Fixed vs. floating point: a surprisingly ...
Design-Reuse

Single- and double-precision IEEE-754 floating-point unit

The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The pipelined design combines high throu ...
Electronic Design

64-bit Floating Point Coprocessor Supports IEEE 754 Calculations

The uM-FPU64 floating point coprocessor chip provides support for IEEE 754-compatible, 64-bit floating point and integer calculations, expanded digital I/O, and analog input capabilities as well as ...
GitHub

Hardware Acceleration using FPGA for Floating-Point Arithmetic

All custom made Verilog modules could complete execution in 1 clock cycle using an Intel Altera Cyclone V 5CSEMA5F31C6N FPGA clocked @ 50 MHz. Note that the CORDIC module was discovered to only be ...